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Description: usb接口协议。It was tested with a USB 1.1 core I have written on
a XESS XCV800 board with a a Philips PDIUSBP11A transceiver.
-usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: |
Size: 11264 |
Author: 颜新卉 |
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Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check for bit unstuffing errors].
Otherwise complete and fully functional.
There is currently no test bench available. This core is very simple
and is proven in hardware. I see no point of writing a test bench at
this time.
Platform: |
Size: 7168 |
Author: eldis |
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Description: usb 2.0 功能模块源代码
usb 1.1 数字物理层源代码-usb 2.0 function core from opencores.org
usb 1.1 phy core
Platform: |
Size: 202752 |
Author: triones |
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Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: |
Size: 196608 |
Author: liang |
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Description: 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
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Size: 43008 |
Author: 天一生水 |
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Description: LTE无线网络仿真平台，涵盖物理层，mac层，和核心网的主要entity，是最新的比较全面的仿真LTE的工具-LTE simulation platform, including PHY, MAC, core network entity.
Platform: |
Size: 14942208 |
Author: naonao |
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Description: 嵌入式串口转以太网控制器，以下简称S2E21，是一款具有高效性能并集成了ARM Cortex-M3微处理器的串行至以太网控制器。该控制器的核心是高度集成的32位Stellaris LM3S6432 ARM Cortex-M3微处理器，具有50MHz性能和96K快速单周期片上闪存及32K SARAM内存，可高效处理网络流量。Stellaris系列微处理器采用LQFP-100 封装，并集成了片上10/100MB以太网MAC和PHY，从而能够最大限度的节省空间。-Embedded Serial to Ethernet controller, hereinafter referred to S2E21, is a highly efficient performance and the integration of ARM Cortex-M3 microprocessor serial-to-Ethernet controller. The controller' s core is a highly integrated 32-bit Stellaris LM3S6432 ARM Cortex-M3 microcontroller with 50MHz single-cycle performance and fast 96K and 32K SARAM on-chip flash memory, can efficiently handle network traffic. Stellaris family of microprocessors LQFP-100 package, and integrates on-chip 10/100MB Ethernet MAC and PHY, allowing maximum space savings.
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Size: 9331712 |
Author: kdlipm |
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Description: USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
Platform: |
Size: 201728 |
Author: 董剑 |
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Description: The RT3052 SOC combines Ralink’s 802.11n draft
compliant 2T2R MAC/BBP/RF, a high performance
384MHz MIPS24KEc CPU core, 5-port integrated
10/100 Ethernet switch/PHY, an USB OTG and a
Gigabit Ethernet MAC. With the RT3052, there are
very few external components required for 2.4GHz
11n wireless products. The RT3052 employs Ralink
2nd generation 11n technologies for longer range and
better throughput. The embedded high performance
CPU can process advanced applications effortlessly,
such as routing, security and VOIP. The USB por t can
be configured to access external storage for Digital
Home applications. In addition, the RT3052 has rich
hardware interfaces (SPI/I2S/I2C/UART/GMAC) to
enable many possible applications.
Platform: |
Size: 3311616 |
Author: Andy |
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Description: The Ethernet IP Core is a MAC (Media Access Controller). It connects to the
Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other.
The core has been designed to offer as much flexibility as possible to all kinds of applications.-The Ethernet IP Core is a MAC (Media Access Controller). It connects to the
Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other.
The core has been designed to offer as much flexibility as possible to all kinds of applications.
Platform: |
Size: 19430400 |
Author: ke |
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Description: PCI Express PIPE Overview-PIPE, which stands for the Physical Interface for PCI Express Specification
developed by Intel, has the stated intent of providing a standard interface between
the internal logic of a PCI Express design and the analog and high-speed circuitry
required to implement the serial link. This purpose of this functional separation is
to allow ASIC and integrated circuit designers to focus on the PCI Express device
core, Transaction, Data Link and logical Physical Layers, while relying on the
PIPE-compliant physical design (PHY) for the electrical interface of the design.
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Size: 103424 |
Author: johnny |
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Description: IP电话专用芯片 The Micrel KSZ8342Q 文档资料。-The Micrel KSZ8342Q Analog Telephone Adapter (ATA) supplies a complete solution for enterprise and residential environments,
converting analog signals from a traditional telephone of fax machine for transmission over IP.
By incorporating an advanced DSP, the KSZ8342Q ATA solution provides all logic necessary for performing analog to digital telephone with connection to IP telephony. The KSZ8342Q ATA device is available in a RoHS-compliant 128-lead QFP package.
The KSZ8342Q ATA device leverages Micrel s core technology competencies including:
• High degree of integration
• Efficient switching
• Low-powered PHY transceivers
• Green design with integrated Energy Efficient Ethernet (EEE)
Platform: |
Size: 1087488 |
Author: dong.jw |
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Description: Generic Phy framework for Linux v2.13.6.
Platform: |
Size: 4096 |
Author: zinqengxie |
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Description: phy-core.c Generic Phy framework.
-phy-core.c Generic Phy framework.
Platform: |
Size: 5120 |
Author: venmuecong |
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Description: Overwrite val to GMII if splitter core is enabled. The phymode here is the actual phy mode on phy hardware, but phy interface EMAC core is GMII.
-Overwrite val to GMII if splitter core is enabled. The phymode here is the actual phy mode on phy hardware, but phy interface EMAC core is GMII.
Platform: |
Size: 3072 |
Author: fhlxpa |
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Description: 1.JESD204B协议
2.Xilinx的JESD204B phy 核手册
3.Xilinx的JESD204B rx_tx 核手册7.1
4.Xilinx的JESD204B rx_tx 核手册7.2
5.verilog实现串口发送(1.JESD204B protocol
2.Xilinx JESD204B PHY core manual
3.Xilinx JESD204B rx_tx core manual 7.1
4.Xilinx JESD204B rx_tx core manual 7.2
5.verilog to achieve serial transmission)
Platform: |
Size: 7014400 |
Author: Nanke42
|
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